1. Field of the Invention
The present invention relates to a simulation apparatus and simulation method used to design the characteristics and circuits of a semiconductor device, and a semiconductor device fabrication method using this simulation method. More specifically, the present invention relates to a simulation technique for a transistor formed in a substrate containing defect states, and a semiconductor device fabrication technique using this simulation technique. Examples of the transistor are a thin-film transistor (TFT) in which a source region and drain region are formed apart from each other in a thin polysilicon film on an insulating substrate, and a gate electrode is formed on a gate insulating film on a channel region between the source and drain regions, and a transistor in which a source region and drain region are formed apart from each other in a polysilicon island region (silicon-on-insulator [SOI]) formed on an insulating substrate, and a gate electrode is formed on a gate insulating film on a channel region between the source and drain regions.
2. Description of the Related Art
In semiconductor device circuit design, circuit characteristics are generally predicted by using a circuit analyzing simulator. The Simulation Program with Integrated Circuit Emphasis (SPICE) created by the University of California, Berkeley (UCB), is most often used as a software tool for use in circuit simulation. A device model used in this simulator is generally called a compact model that is simplified in order to obtain calculation results within a relatively short time.
Under such circumstances, for a metal oxide semiconductor (MOS) transistor that changes the impedance between the source and drain regions by controlling the surface charge density of a semiconductor layer by changing its surface potential by the gate voltage, a general approach is to use different voltage-current expressions in a weak inversion region (subthreshold—weak inversion region) in which the gate voltage is relatively low and the drain current starts flowing and a strong inversion region in which the gate voltage is sufficiently high and the drain current is large.
Representative transistor models derived from this technical approach are a series called Berkeley Short-Channel IGFET Model (BSIM) (e.g., BSIM 4.3.0 MOSFET Model, User's Manual, Department of Electrical Engineering and Computer Science, University of California, Berkeley, Calif. [2003]). Of the drain current as the sum of a diffusion current and drift current, these models use only the diffusion current in the weak inversion region where the diffusion current component is dominant, and use only the drift current in the strong inversion region where the drift current is dominant.
That is, diffusion current approximation is performed in the weak inversion region as indicated by
      I    D    =            I      on        ⁢          exp      (                                    V            GS                    -                      V            on                                    ζ          ⁢                                          ⁢                      V            T                              )      
Drift current approximation is performed in the strong inversion region as indicated by
      I    D    =      μ    ⁢                  ⁢          C      ox        ⁢          W      L        ⁢          {                                    (                                          V                GS                            -                              V                                  TH                  ⁢                                                                          ⁢                  0                                                      )                    ⁢                      V            DS                          -                              V            DS            2                    2                -                              2            3                    ⁢                      γ            ⁡                          [                                                                    (                                                                  V                        DS                                            -                                              V                        BS                                            +                                              2                        ⁢                                                  ϕ                          F                                                                                      )                                                        3                    2                                                  -                                                      (                                                                  -                                                  V                          BS                                                                    +                                              2                        ⁢                                                  ϕ                          F                                                                                      )                                                        3                    2                                                              ]                                          }      where ID is the drain current, Ion is a diffusion current exponential function coefficient, VGS is the gate-to-source voltage, Von is the diffusion current offset voltage, ζ is a diffusion current thermal voltage coefficient, VT is the thermal voltage, μ is the carrier mobility, Cox is the gate oxide film capacitance, W is the channel width, L is the channel length, VTH0 is the threshold voltage, VDS is the drain-to-source voltage, γ is a coefficient of the substrate biasing effect, VBS is the substrate (bulk)-to-source voltage, and φF is the Fermi level.
Using different expressions to calculate currents in different operating regions as described above simplifies the expressions and facilitates the analysis. This makes it possible to advantageously shorten the calculation time.
In a so-called piece-wise model (level 2 SPICE model, to be referred to as a drift model hereinafter) that changes the voltage-current expression in accordance with an operating region, however, as shown in FIG. 20A, the differential value of a current is discontinuous in the boundary (hatched region near threshold voltage VTH of a transistor) between the weak inversion region and strong inversion region. As a consequence, a large error as shown in FIG. 20B may occur in this boundary, so approximation is performed by using a qualitatively correct curve as shown in FIG. 20C.
The piece-wise model, therefore, is inconvenient for the analysis of, e.g., an analog circuit that operates from the weak inversion region to the strong inversion region. Also, since the channel length has recently decreased to about 100 nm, the reliability of the drift model has decreased.
Accordingly, attempts have been made to solve the drift diffusion model expression as the basic expression of a current without separating the expression in accordance with an operating region. A representative attempt is a model called the Hiroshima University STARC IGFET Model (HiSIM). This model uses a method of calculating the surface charge by deriving the surface potential by a single expression (diffusion-drift expression) in the operation from weak inversion to strong inversion of a transistor (MOSFET), thereby obtaining a current. M. Miura-Mattausch et al., “Unified complete MOSFET model for analysis of digital and analog circuits”, IEEE Trans. CAD/ICAS vol. 15, pp. 1-7 (1996) describes that the voltage-current characteristic of a MOSFET obtained by this method can extremely well reproduce a measured value.
The technique that forms amorphous silicon (amorphous-Si) on an insulating substrate such as a glass substrate and forms polysilicon close to single-crystal silicon by using the laser crystallization technique has recently advanced. Attempts that integrate functional circuits in this polysilicon substrate or amorphous silicon substrate have been extensively made. Incorporating circuits in the polysilicon substrate or amorphous silicon substrate eliminates disconnection at circuit connecting points and the like. This increases the reliability and reduces the fabrication cost.
At present, however, it is still difficult to obtain perfect single-crystal silicon even by using the laser crystallization technique. As shown in FIG. 21A, polysilicon contains many single-crystal silicon grains having various plane orientations, and trap states (defect states or localized states) for trapping carriers exist in the grain boundaries. Also, amorphous silicon has many localized states. Furthermore, interface states resulting from dangling bonds of a silicon crystal exist in the interface between a silicon layer and an oxide film in contact with the silicon layer. In addition, the formation temperature of an oxide film formed on polysilicon or amorphous silicon on a glass substrate is as low as about 500° C. This makes the number of interface states immeasurably larger than that of an ordinary MOSFET.
When the localized states or interface states as described above exist, the physical mechanisms of device operations complicate. The present circuit analyzing models for insulated-gate transistors using polysilicon or amorphous silicon are not models of these physical mechanisms, but models that merely introduce fitting parameters for simply fitting the physical properties of devices. Accordingly, these models have low accuracy and are not necessarily satisfactory.
This is so because the operation model of an insulated-gate transistor containing localized states is not necessarily based on a physical model, but uses simple fitting parameters for simulating measured device characteristics.
Since the operation model is not based on a physical model, if the channel length or the like has changed, prototype devices having the same channel length are fabricated, and the device parameters are extracted. Following this procedure prolongs the time necessary to obtain an accurate circuit analyzing device model. Also, for an insulated-gate transistor using polysilicon or amorphous silicon having a physical mechanism more complicated than that of single-crystal silicon, the number of parameters of a device model often increases, so there is no convenient device model.
As described above, for a TFT formed in a polysilicon layer on an insulating substrate or for a transistor formed on an SOI substrate, there is no circuit model based on a physical model including defect states, and many fitting parameters are necessary. Accordingly, it takes a long time to obtain an accurate circuit analyzing device model. For a transistor formed in polysilicon or amorphous silicon, therefore, the number of parameters of a device model increases, and this makes the device model inconvenient.